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| idt | the analog + digital company idt serial rapidio switch feature comparison i nteg rated de vice te ch nology idt serial rapidio ? switch feature comparisonchart features cps-1848 CPS-1432 cps/sps-1616 cps-6q /10q cps-8 / 12 / 16 tsi572 / 574 / 578 tsi577 tsi620 performance and confgurability serial rapidio specifcations 2.1 2.1 2.1 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 aggregate peak throughput (gbps) 240 160 80 60 100 20 30 40 30 40 80 40 50 full mesh non-blocking fabric f f f f f f f f f f f f asymmetric non-blocking fabric f maximum of number of x4 ports 12 8 4 6 10 2 3 4 2 4 8 4 3 maximum of number of x2 ports 18 14 8 maximum of number of x1 port 18 14 16 16 16 8 12 16 8 8 16 16 6 cut-through latency (ns) 100 100 100 190 190 190 190 190 110 110 110 110 110 store and forward mode f f f f f f f f f f f f f confgurable by speed each quad each quad cps/sps - each lane each quad each quad each lane pair each mac each quad each mac serdes and power power per 10 gbps link (typical, mw) <300 <385 cps/sps <440 <500 <500 <500 <500 <500 identical long and short reach power f f f f f per port power down f f f f f f f f f f f f f programmable transmit drive strength and pre-emphasis f f f f f f f f f f f f f programmable receive equalization f f f f f f f f on-die scope capability f f f f f multicast and routing per port multicast architecture f f f f f f f f parallel multicast engine with qos support f f f f f per port multicast masks/groups 40 40 40 40 40 10 10 10 8 8 8 8 8 8- and 16-bit addressing f f f f f f f f f f f f f programmable watermarks on ingress bufers f f f f f f f f f f f f f rapidio standard and non-standard features packet/trace/mirror/ flter for debug f f f f f f f f trafc management through user selectable scheduling algorithms f f f f f f f f receiver controlled fow control f f f f f f f f f f f f f transmitter controlled fow control f f f performance counters/monitors f f f f f f f f f f f f f dedicated maintenance path for 5th priority f f f f f f f f error management features exceeding s-rio specifcation f f f f f f f f error log (history) and broad error detection coverage f f f f f f f f link-layer aes-128 encryption sps on 4 1x ports bom reduction and clocking options clocking options (mhz) 156 156 156 156 156 156 or 125 156 or 125 156 or 125 no power-up sequence or ramp rate requirements f f f f f run rapidio at cpri and obsai speeds f f f f f lane swap for board design simplifcation f f f f f debug packet generator f f f f f f f f debug packet capture f f f f other bridging and unique features built-in hardware bridging from rapidio to pci f built-in bridging options to non-serdes fpga f package (mm) 29 x 29 25 x 25 21 x 21 27 x 27 27 x 27 19 x 19 19 x 19 19 x 19 21 x 21 21 x 21 27 x 27 21 x 21 27 x 27 gd_s-rio switches_revb0311
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